Senior Engineer - Characterization

Characterize the performance of IP custom cells and optimize the cell design and layout. Characterization and modeling of Custom cells to provide timing/power model for verification. Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality. Develop automation test bench/flow/tools to improve the work efficiency and help data analysis. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in Siliconsmart, Liberate, Liberate_LV, Primetime ,Solido Analytics and Cadence Virtuoso preferred. Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Analog block design and verification preferred. Experience in Standard Cell design and verification Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis is a plus Previous work experience in DRAM memory related fields is a plus. Must possess good communication skills and ability to work well in a team Bachelor's or Post Graduate Degree in Electronics Engineering or related engineering field with 3+ years Industry relevant experience required