Senior Engineer, DPG IP DEV Layout

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. 3 to 7 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc. Ability to understand design constraints and implement high-quality layouts Ability to understand design hierarchy and different architectures for Memory designs. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks. BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.