Senior Engineer, Scribe Design

Req. ID:\n\nJR98050 Senior Engineer, Scribe Design\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nMicron Technology\u2019s vision is to transform how the world uses information to enrich life and our dedication to people, innovation, tenacity, teamwork, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. We are the only company manufacturing today\u0027s major memory and storage technologies: DRAM, NAND and Emerging memory.\n\nWe are looking for an energetic, ambitious, result-driven individual with strong work ethic and integrity to join us as the Scribe Design Engineer. The Scribe Design Non-Array (SDNA) team is responsible for the design, layout, and verification of CMOS electrical test structures that enable CMOS device development, Compact modeling, Reliability modeling and Fab process monitoring.\n\nIn this role you will work with a group of Engineers in India, Japan, and the US. As part of a global team, you will contribute to physical layout, floor planning and verifying through DRC and in-house verification tools. This role will allow you to work on all technology types at Micron.\n\nSpecific responsibilities include but not limited to:\n\n * Understand the technology challenges, work with partner groups to provide CMOS Test Structure design and layout solution for N, N+1 and N+2 process technology nodes\n * Verify integrity of the TEG design through LVS, DRC, E-simulation, and in-house verification tools\n * Be a strong customer interface to maintain high customer satisfaction.\n * Attend necessary area meetings to understand the scope and Coordinate activities related to Scribe scheduling, design, improvement and Tape Out.\n * Learn and apply Micron Layout methodology, simulations and automation for TEG solutions.\n * Understand the Fab Quality performance of our Scribe designs\n * Strive to continuously improve the accuracy and repeatability of our Structures\n * Use Metrics and data to drive decisions and improve performance.\n * Provide advice and counsel to senior management on significant technical issues related to CMOS TEG design solutions and automation.\n * Define and lead complex and multi-disciplinary projects that are critical for SCRIBE Design solutions\n\n\n\nQualifications for this position include:\n\n * Hands on experience and proficiency in EDA tools (Cadence Virtuoso Layout and Schematic Editor, Calibre,Hspice etc.)\n * Layout and Verification skills in Cadence and Calibre (DRC, LVS)\n * Able to run pre and post simulations (Hspice/Finesim) and analyze the simulations with silicon data.\n * Good knowledge of semiconductor device physics, operation, parametric testing and DFM.\n * Strong understanding micron memory process\n * Good project management skills\n * Overview of fab process steps and overall wafer fabrication processes \u2013 Familiarity with device characterization is a plus.\n * Familiarity with linux/unix system and scripting languages Phyton/Skill is a plus.\n * Demonstrated innovative problem-solving skills.\n * Willingness to learn new skills and explore unfamiliar concepts.\n * Ability to develop and maintain relation with cross-functional teams and partners.\n * Good oral and written communication skills to interact with global and local teams.\n\n\n\nEducation \u0026 Experience requirements: \n\n * BE/B.Tech in with at least 6 years of relevant experience\n * ME/M.Tech in Electrical or Electronics Engineering or other similar discipline with at least 4 years of relevant experience\n\n\n\nJob Profile(s):\n\nSemiconductor Design Engineer 3\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n