Senior Engineer SoC Validation

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor's degree in Electronics/Electrical Engineering, Computer Science, Information Systems, or related field. 4+ years Hardware Engineering experience or related work experience. Basics of ARM SoC architecture, Multicore/Multiprocessor with SMP/MTE/heterogeneous cores. C language expertise for low level programming, Assembly language for any processor, C-assembly interworking. Hands on python / C# programming, test automation programming, remote debugging, Using JTAG based debuggers, compilers/linkers. Exposure to boot process, MMU, page tables. Operating systems/RTOS/Linux kernel internals. Bash scripting, SW application development. Exposure to working on programming for DFT and RF modem characterization environment is added advantage. Exposure to working on emulation/pre-si environment is added advantage Using JTAG based debuggers, compilers/linkers Should have good exposure to software development life cycle - Exposure to SoC architecture paradigms - interconnects, power management, - Software development for silicon enablement, silicon validation - Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs - Software for power/performance KPIs - Good knowledge of ARM Cortex-A7/A8) / x86 / PowerPC CPU and memory system architecture - Weakly ordered memory model/pipelining of memory systems/memory barriers - Software development towards higher performance of multi-threaded applications using lower power - Top level of ASIC design methodology is an added skill You will be working with IP validation teams and Systems validation Lead/system content engineer for bring up the framework. Own SoC frequent regression and execute end-to-end regression suite by considering SoC design corner cases w.r.t power and performance. Executing these releases on bench in lab and supporting the DFT,SLT teams in Debug and enabling different features in the framework. Work with a relevant team member for regular reporting of issues and failure debugs.