Senior Layout Engineer-DPG-LPDDR

Req. ID:\n\nJR95562 Senior Layout Engineer-DPG-LPDDR\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRoles and Responsibilities\n\n * Own the layout and integration of critical analog blocks, ensuring low\u2011noise performance, high reliability, and robust operation across PVT corners for advanced process technologies.\n * 6+ years of hands\u2011on experience in custom analog / mixed\u2011signal layout\n * Apply strong device physics expertise to drive high\u2011quality layout implementation, including transistor matching strategies, well and substrate engineering, parasitic optimization, and EM/ESD reliability considerations.\n * Execute and review high\u2011speed layout techniques for sensitive analog and mixed\u2011signal paths, focusing on impedance control, skew matching, shielding, isolation, and crosstalk mitigation.\n * Work closely with circuit designers and architects to enable layout\u2011aware design, proactively identifying and resolving parasitic, noise, and performance risks early in the design cycle.\n * Lead post\u2011layout optimization and sign\u2011off activities, including DRC/LVS, EM/IR analysis, and correlation of post\u2011layout simulations with silicon or lab data.\n * Provide technical guidance and design reviews for complex blocks, contributing to best practices, quality improvement, and first\u2011silicon success.\n * Leverage AI/ML knowledge as a value\u2011add to support data\u2011driven optimization, layout automation initiatives, and improved debug and correlation workflows.\n\n\n\nEducation\n\n * B.E. / B.Tech in Electronics, Electronics \u0026 Communication, or VLSI Engineering\n * M.Tech in VLSI Design, Microelectronics, or Electronics Engineering\n\n\n\nJob Profile(s):\n\nSemiconductor Design Engineer 3\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n