Senior Lead Engineer Digital Verification

• 4+ years of design verification experience.
• BS (or higher) in EE/EC/ECC Engineering
• Experience in mentoring junior engineer
• Must have excellent knowledge of computer architecture and design verification fundamentals
• Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
• Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology
• Experience in Low Power Simulation/UPF setup, debug low power simulation failures.
• Exposure to Wired or Wireless Technologies: PCIe, USB, Ethernet, 5G, WiFi, MAC layer or PHY/DSP layer
• Exposure to scripting languages like Perl, Unix shell or similar languages
• Good to have some experience with assembly language programming required
• Excellent written and oral communication skills necessary
• Candidate must be self-motivated and capable of working independently or as part of a team
• Nice to have hands-on on for Wifi 802.11 MAC layper protocol

#LI-DNI