Senior Physical Design Engineer, DPG

Req. ID:\n\nJR97432 Senior Physical Design Engineer, DPG\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\n\n * Own end-to-end physical implementation for SoC blocks and/or top-level designs, including floor planning, placement, clock tree synthesis (CTS), routing and physical optimization, to achieve power, performance, and area (PPA) targets.\n * Lead timing closure (setup/hold) across complex multi-mode, multi-corner (MMMC) scenarios, partnering closely with RTL, micro-architecture, STA, and signoff teams to drive convergence to timing-clean designs.\n * Collaborate with design, integration, and system teams to ensure robust implementation of clocking and reset strategies, power intent (UPF/CPF), low-power features, and SoC integration requirements.\n * Collaborate with CAD, methodology, and technology teams to identify and fix tool, flow, and process-related implementation challenges. Support adoption of new nodes and develop methodologies.\n * Perform and/or coordinate physical signoff activities, including DRC/LVS, IR drop, EM reliability, noise, and timing signoff, driving efficient closure of violations with minimal schedule impact.\n * Complete and support tape-out readiness, including signoff checklists, ECO implementation, risk reviews, and final release activities, ensuring alignment with quality and schedule commitments.\n * Contribute to post-silicon debug and silicon bring-up, correlating silicon behavior with physical invent, STA, and power analysis to root-cause issues and feed findings back into build flows.\n * Identify flow gaps, quality risks, and scalability challenges, and improve productivity through scripting, automation, and development of best-practice methodologies.\n\n\n\nJob Requirements\n\n * 4\u20138 years of hands-on experience in physical design implementation for complex SoC or large-scale digital blocks, with proven ownership from initial floorplanning through tape-out.\n * Strong experience in block-level timing analysis and closure, including setup/hold closure across multi-mode, multi-corner (MMMC) scenarios, in collaboration with STA and signoff teams.\n * Proven experience working on advanced process technology nodes (e.g., 5nm, 3nm, or equivalent), with awareness of node-specific physical design challenges and constraints.\n * Proficiency with industry-standard place-and-route tools such as Cadence Innovus and/or Synopsys IC Compiler II, including ECO implementation and design optimization.\n * Hands-on expertise in physical verification and signoff closure, including DRC, LVS, antenna, and related foundry checks, with the ability to efficiently debug and resolve violations.\n * Strong understanding of power integrity and reliability analysis, including IR drop, electro-migration (EM), noise, coupling, and crosstalk, along with effective mitigation strategies.\n * Demonstrated ability to analyze IR/EM issues at the block level and close them. Collaboration with power, signoff, and engineering groups happens based on feedback and analysis results.\n * Solid foundation in digital design fundamentals, including digital electronics, microprocessors, and computer architecture, enabling effective collaboration with RTL and architecture teams.\n * Experience in bringing to bear automation and scripting (e.g., Tcl, Python, or equivalent) to improve physical develop efficiency, quality, and turnaround time.\n * Exposure to AI-assisted tools and workflows, including timely engineering or analysis supported by AI, to improve debugging, optimization, or efficiency in physical development flows.\n * Proven ability to mentor and guide less-experienced engineers, contributing to technical skill development, build reviews, and sharing effective approaches within the team.\n\n\n\nEducation\n\n * B.Tech in Electronics, Electronics \u0026 Communication, or VLSI Engineering, or equivalent experience\n * M.Tech in VLSI Design, Microelectronics, or Electronics Engineering\n\n\n\nJob Profile(s):\n\nSemiconductor Design Engineer 3\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n