Senior Staff DFT MBIST Engineer

Role Overview

We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator SoCs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced SoC designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.

This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.

Location:

Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.

Key Responsibilities

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  Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.

  
  


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  Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.

  
  


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  Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.

  
  


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  Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.

  
  


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  Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).

  
  


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  Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.

  
  


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  Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.

  
  


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  Perform detailed ATPG coverage analysis and drive coverage closure.

  
  


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  Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.

  
  


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  Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.

  
  


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  Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.

  
  

Minimum Qualifications

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  BE/ME (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

  
  


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  7+ years of experience in DFT, including scan test and MBIST.

  
  


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  Proficiency with HDLs such as Verilog, SystemVerilog, or VHDL.

  
  


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  Experience with scripting or programming languages (e.g., Python, Perl, TCL, C).

  
  


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  Strong ability to collaborate effectively in cross-functional and diverse teams.

  
  


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  Experience producing clear, detailed technical documentation.