Senior/ Staff/ Principal - Silicon Design Validation Engineer

Solid understanding & experience of Analog VLSI Design is crucial Demonstrated ability to head technical task forces with accountability and ownership is crucial NAND product design development, validation, characterization & qualification preferred Experience in simulation as well as debugging silicon signals from bench testing Previous experience with hands-on measurements on wafer probe stations and testers for invent validation is beneficial Drive timely issue resolution with multi-functional teams (Probe & Design Engineering) for improved validation & root cause understanding Excellent data analysis, problem solving, and decision-making skills Solid base of mixed-signal VLSI such as analog circuits and systems, digital logic and RTL design. Understanding of Flash memory architecture and operation Proficiency in bench testing equipment (o-scope, logic analyzer, Nextest Magnum, etc) is valuable Knowledge in writing testbenches in SV, Verilog, Verilog-AMS, Spice would be beneficial Fundamental programming/scripting skills (C/C++, Python, Perl, Verilog) Effective communication and presentation skills Experience in device modelling in TCAD and MATLAB and Device Fabrication will be beneficial Strong fundamentals in Analog VLSI design preferred Tools knowledge: Teradyne's Magnum, Verilog, ModelSim, Cadence Virtuoso, Oscilloscope Python, C skills would be an added advantage This role mandates a master's degree or equivalent experience in electrical engineering, Computer Engineering or related fields + 8 years' experience Course work in VLSI technology, analog/digital circuits, semiconductor process and semiconductor device physics