SMTS ASIC Architect

Req. ID:\n\nJR96793 SMTS ASIC Architect\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole Overview\n\nThe DRAM ASIC Architecture team defines silicon level architectures that extend and differentiate the value of Micron\u2019s DRAM products. The team works across technology generations and product lines, collaborating closely with design, product, systems, and ecosystem partners to deliver scalable, reliable, and high-performance memory solutions aligned with customer and market needs.\n\nAs a Senior Member of Technical Staff, you will provide senior level architectural leadership for ASIC and logic-based DRAM solutions that emphasize high bandwidth, energy efficiency, scalability, and reliability. This role spans near term product execution and long term technology direction, with architectural ownership over decisions that impact bandwidth density, latency, RAS, and system observability.\n\nKey Responsibilities\n\n * High\u2011Bandwidth DRAM Architecture\n * Define ASIC and logic architectures that enable high data throughput, efficient parallelism, and scalable bandwidth delivery for advanced DRAM products.\n * Drive architectural features that improve effective bandwidth, latency efficiency, and utilization under demanding workloads.\n * Silicon\u2013Package\u2013System Co\u2011Optimization\n * Lead architectural trade\u2011off analyses across DRAM silicon, ASIC logic, packaging constraints, and system integration considerations.\n * Ensure architectural choices account for power delivery, thermals, signal integrity, and form\u2011factor limitations.\n * Architectural Partitioning \u0026 Interfaces\n * Influence functional partitioning and interface definition across DRAM devices and associated logic to optimize performance, power, and scalability.\n * Contribute to definition of robust, scalable interfaces and protocols that support high data rates and reliable operation.\n * Silicon Architecture Analysis\n * Drive architectural analysis including PPA evaluation, IO timing considerations, and scalability paths for next\u2011generation DRAM products.\n * Establish architectural guardrails that enable reuse and extensibility across product families and technology nodes.\n * Technical Quality \u0026 First\u2011Silicon Success\n * Perform micro\u2011architectural, RTL, and design reviews, along with verification and coverage reviews, to ensure high\u2011quality execution and first\u2011silicon success.\n * Proactively identify architectural risks and guide mitigation strategies in collaboration with design and validation teams.\n * Technical Leadership \u0026 Mentorship\n * Serve as a technical mentor and architectural authority for execution teams, elevating technical rigor and design quality.\n * Influence cross\u2011functional decisions through clear reasoning, data\u2011driven analysis, and deep architectural insight.\n\n\n\nMinimum Qualifications\n\n * Bachelor\u2019s degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n * Extensive professional experience in DRAM die architecture, including deep understanding of architectural trade\u2011offs affecting bandwidth, latency, power efficiency, and reliability (RAS).\n * Proven experience leading micro\u2011architectural and architectural decisions on complex memory subsystems or silicon solutions, from specification through product delivery.\n\n\n\nPreferred Qualifications\n\n * Master\u2019s or PhD degree (or equivalent experience) in a relevant engineering or computer science field.\n * Experience collaborating across multiple technical domains such as DRAM silicon, ASIC logic, packaging, high\u2011speed interfaces, or system architecture.\n * Experience engaging with customers, ecosystem partners, or industry standards organizations (e.g., JEDEC).\n * Demonstrated technical leadership across multiple projects or product generations.\n * Familiarity with system\u2011level tradeoffs involving performance, power, signal integrity, thermals, or cost.\n\n\n\nJob Profile(s):\n\nSystems Design Engineering SMTS\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n