Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

Req. ID:\n\nJR95830 Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nAdvanced Packaging Technology Development org is seeking an experienced and technically strong Semiconductor design Senior Engineer to support High Bandwidth Memory (HBM) packaging program. This role sits at the critical intersection of silicon design and advanced packaging, responsible for executing advanced packaging related design strategy that enables world-class HBM product integration. In this position, you will collaborate with Micron\u2019s various design teams HIG DTPCO, DRAM designers all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction\n\nKey Responsibilities\n\n\u2022 PWF Reticles Design and tapeout\n\n\u2022 Developing DFTs in test vehicles for packaging related fail modes\n\n\u2022 Co-work with HIG-HBM DTPCO, HIG-HBM team for developing test structures for live die\n\n\u2022 Design rules management, Process Design rules for PWF , wafer thinning and dicing, die stacking etc\n\n\u2022 BEOL Design - mainly engagement with FE Integration teams\n\n\u2022 Engagement with Scribe Design team to capture Advanced Packaging requirements and Review\n\n\u2022 TSV design engagement with HIG-HBM DTPCO teams ( electrical , thermal and mechanical performance)\n\n\u2022 Creationand Maintenance of DFMEA related to advacned packaging process steps like PWF, die stacking etc\n\n\u2022 Perform Electrical Simulations to understand the fail mode mechanism \n\n \nRequired Qualifications\n\n \nEducation \n\u2219 Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field required \n \nExperience \n\u2219 5+ years of experience in die design and physical layout engineering \n\u2219 Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent) \n\u2219 Proven experience with TSV-based die design including KOZ management, micro-bump layout, and backside RDL\n\n \nTechnical Skills \n\u2219 Deep expertise in physical design and layout using industry-standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler) \n\u2219 Strong knowledge of DRC/LVS/ERC sign-off flows and foundry PDK rule interpretation \n\u2219 Solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints \n\u2219 Working knowledge of DFT structures relevant to advanced packaging: daisy chains, BIST, boundary scan, IEEE P1838 \n\u2219 Familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E) \n\u2219 Understanding of power integrity, signal integrity, and thermal considerations at the die-package interface \n\u2219 Experience with parasitic extraction and layout-driven optimization for high-speed memory interfaces \n \nPreferred Qualifications\n\n \n\u2219 Experience with hybrid bonding or direct bond interconnect (DBI) die design constraints \n\u2219 Familiarity with chiplet architecture and disaggregated die design for heterogeneous integration \n\u2219 Knowledge of HBM assembly (TCB, underfill, wafer thinning) \n\u2219 Experience with layout automation scripting (Skill, Python, Tcl) for template generation and DRC waiver management \n\u2219 Exposure to reliability physics relevant to advanced packaging: electromigration, stress voiding, thermo-mechanical degradation \n\u2219 Published work or patents in advanced packaging, 3D-IC design, or memory interface design\n\nJob Profile(s):\n\nSemiconductor Design Engineer 3 - Semiconductor Design Engineer 4\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n