SR Engineer, ASIC DFT

Req. ID:\n\nJR96815 SR Engineer, ASIC DFT\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nMicron is awarded as a Great Place to Work! We focus on innovation through Integrity and inclusion. We are proud to have a set of core values(People, Innovation, Tenacity, Collaboration and Customer Focus) which is reflected in our culture! Micron is a diverse organization of dedicated and innovative individuals, and we provide equal opportunities to all. At Micron, we don\u0027t discriminate on the basis of race, color, religion, gender, sexual orientation, disability, identity, national origin, or status as a protected veteran.\n\nAs a Micron\u0027s ASIC DFT team we implement DFT for Micron IPs and Memory controllers(SOC) developed for different type of Storage products in Micron. We are using the best in class DFT methodologies and process technologies to ensure that we deliver the best quality products to achieve the lowest DPPM numbers.\n\nWe work closely with Design(RTL), DV, Physical Implementation team, Test Engineering and Product Engineering team to support early analysis to the Silicon bring-up and Characterization.\n\n## Required Skills and Experience :\n\nBachelor\u2019s or Master\u2019s Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs :\n\n * Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN \u0026 JTAG (IEEE1149.1 \u0026 IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis.\n * Must have experience with Siemens, Synopsys and/or Cadence Cad tools.\n * Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python.\n\n\n\nResponsibilities -\n\n * Accountable for innovative DFT implementation(Scan, MBIST, LBIST \u0026 Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.\n * Generate and validate ATPG patterns using simulations.\n * Shall Validate the DFT implementation using RTL and Gate level simulation.\n * Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification \u0026 Validation.\n * Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program.\n * Chip in to the overall DFT methodology development.\n\n\n\nNice to have Skills/Experience :-\n\n * Shall have Knowledge of IEEE 1149.6, 1500 and 1838.\n * Good experience on Hierarchical Scan implementations with core wrapping concepts\n * Experience in handling multi-clock domains and low power design implementation.\n * Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation.\n * Communicate effusively with multi-functional functional teams in different geographies and time Zones.\n * Time management and multi-tasking skills.\n\n\n\n## Job Location:\n\nYou will be joining part of growing team in Hyderabad or Bangalore. We value People and our dedication is to reward people with multiple Micron benefits that include PTO and medical benefits to name the few.\n\nJob Profile(s):\n\nASIC Engineer 3\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n