Sr Engineer - DEMQRA WLR

Wafer Level & Package Level Reliability testing & analysis for CMOS & Interconnects. Comprehend failure modes and failure rate within the scope of the product qualification. Perform risk assessment at all decision points within qualification cycle. Provide WLR support for HVM Fab Process conversion & Excursion material disposition. Collaborate with Technology Development for new technology node deployment. Develop process reliability tests to assess new process failure mechanisms. Ensure that test methodology follows industry standards, such as the Joint Electron Devices Engineering Council (JEDEC). Experience in handling Package Level / Wafer Level Reliability Systems or Parametric analyzers or Semiconductor characterization. Strong background in Intrinsic Semiconductor Reliability Failure Mechanisms and product fail modes. Familiarity with statistical concepts relevant to semiconductor reliability. Good understanding of CMOS Device Engineering, process integration and Statistical Quality Control. Excellent data analysis and problem solving skills. Bachelors with 2+ years experience or Masters in Electrical Engineering / Microelectronics / Nanotechnology / Material Science Engineering.