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Sr Layout Engineer-DPG LPDDR

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Job Description - Sr Layout Engineer-DPG LPDDR

Req. ID:\n\nJR96870 Sr Layout Engineer-DPG LPDDR\n\nOur vision is to transform how the world uses information to enrich life for all.\n\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\n\nPlace \u0026 Route / Physical Design\n\n * place-and-route (P\u0026R) and layout closure for digital or semi\u2011custom blocks.\n * Develop floorplans, power grids, and placement strategies\n * Leverage AI\u2011assisted RTL\u2011to\u2011GDS flows for early PPA prediction, congestion awareness, and faster convergence\n * Execute placement, CTS, and routing using industry\u2011standard PnR tools\n * Drive timing, power, and congestion closure\n * Fix DRC, LVS, antenna, EM/IR violations to achieve signoff\u2011clean designs\n * Apply AI\u2011guided ECO generation and prioritization for timing, power, and functional fixes.\n * Collaborate with RTL, DFT, STA, and signoff teams during the design cycle\n * Support tape\u2011out and post\u2011silicon debug activities\n\n\n\nStatic Timing Analysis (STA)\n\n * Perform full\u2011chip and block\u2011level STA across all modes, corners, and scenarios\n * Analyze and close setup, hold, recovery, removal, and pulse width checks\n * Perform pre\u2011CTS and post\u2011CTS timing analysis\n * Work closely with PnR teams to drive timing closure strategies\n * Handle OCV/AOCV/POCV, CRPR, and clock uncertainty modeling\n * Analyze and debug timing paths, false paths, and multicycle paths\n * Perform timing ECO recommendations and validate fixes\n * Generate and review timing reports for signoff\n * Support timing signoff using foundry\u2011qualified methodologies\n\n\n\nJob Profile(s):\n\nLayout/Mask Designer E3\n\nRelocation level: (TBD)\n\nBefore Getting Started \nPlease review Micron\u2019s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: \n\n * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.\n * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.\n\n\n\n\u200b\u200b\u200b\u200b\n\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc\n\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\n
Original job Sr Layout Engineer-DPG LPDDR posted on GrabJobs ©. To flag any issues with this job please use the Report Job button on GrabJobs.
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