Sr.Manager//Sr. Architect - ASIC RTL // 6-22 yrs //Pan India

Job Opening: Senior Manager/Senior Architect - ASIC RTL

Location: Pan India

Job Description:

Required Skills:

• Expertise in SoC subsystem/IP design
  
• Proficiency in IP design, Subsystem/Cluster, and SoC level integration using Verilog/System Verilog
  
• In-depth knowledge of RTL quality checks (Lint, CDC)
  
• Familiarity with synthesis and low power is a plus
  
• Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
  
• Proficiency in timing concepts
  
• Knowledge of one or more interface protocols: PCIe, DDR, Ethernet, I2C, UART, SPI
  
• Experience in setting up and using tools like Spyglass Lint/CDC, Synopsys DC, Verdi/Xcellium
  
• Understanding of scripting languages such as Make flow, Perl, shell, Python, etc.
  
• Familiarity with processor architecture and/or ARM debug architecture is advantageous
  
• Ability to assist and debug issues for multiple subsystems
  
• Capability to create/review design documents for multiple subsystems
  
• Support for physical design, verification, DFT, and SW teams on design queries and reviews
  

• 6-22 years of experience
  
• Proficiency in RTL, Coding, design, IP design, SOC Development, Lint, CDC, Micro Architecture