STA Engineer

Key Responsibilities:

• Static Timing Analysis (STA):

• Perform comprehensive timing analysis using tools like NanoTime for advanced process nodes (2nm/3nm).

• Develop and validate timing constraints for high -performance designs.

• Identify and resolve timing bottlenecks to ensure optimal performance, power, and area.

• Circuit Simulation:

• Conduct SPICE simulations for analog, mixed -signal, and digital circuits to verify functionality and performance.

• Analyze circuit behavior, including power, noise, and signal integrity, across process, voltage, and temperature corners.

• Collaboration and Debugging:

• Work closely with RTL designers, layout engineers, and physical design teams to ensure seamless integration and silicon success.

• Debug and resolve timing or simulation issues identified during the design or validation phase.

• Optimization and Verification:

• Optimize designs to meet timing, power, and area requirements specific to 2nm/3nm TSMC technologies.

• Perform pre - and post -layout simulations to ensure accuracy and compliance with design specifications.

Requirements

• Educational Background:

• Bachelor’s/Master’s/Ph.D. in Electrical Engineering, Microelectronics, or a related field.

• Experience:

• 3+ years of experience in STA and SPICE simulation, preferably for advanced process nodes.

• Hands -on experience with 2nm/3nm process technologies and familiarity with TSMC PDKs is highly preferred.

• Technical Skills:

• Proficiency in NanoTime and industry -standard SPICE simulation tools (e.g., HSPICE, Spectre).

• Strong understanding of timing analysis methodologies, signal integrity, and noise analysis.

• Knowledge of process variations and their impact on timing and circuit performance.

• Familiarity with DRC, LVS, and parasitic extraction flows.

• Soft Skills:

• Strong analytical and problem -solving skills.

• Excellent communication and collaboration abilities.

• Ability to work independently in a fast -paced, innovative environment.