STA Engineer (Static Timing Analysis)

This role is for one of the Weekday's clients

Salary range: Rs 1200000 - Rs 2000000 (ie INR 12-20 LPA)

Min Experience: 5 years

Location: Bangalore

JobType: full-time

We are seeking an experienced Static Timing Analysis (STA) Engineer to play a critical role in ensuring timing integrity and performance for advanced ASIC and SoC designs. In this role, you will be responsible for performing detailed timing analysis and supporting timing closure across block-level and full-chip designs. You will work closely with RTL, Physical Design, and verification teams to identify, analyze, and resolve timing violations while ensuring designs meet required performance and power targets. The position requires strong expertise in timing methodologies, constraint management, and signoff processes using industry-standard EDA tools. You will contribute to debugging complex timing issues across multiple operating corners and modes while ensuring the design meets stringent signoff requirements. This role offers the opportunity to work on advanced semiconductor technologies and collaborate with cross-functional teams to deliver high-quality silicon. The ideal candidate is highly analytical, detail-oriented, and experienced in optimizing timing performance across complex ASIC or SoC architectures while maintaining strong collaboration with design and implementation teams.

Key Responsibilities

• Perform Static Timing Analysis (STA) for both block-level and full-chip ASIC/SoC designs
• Analyze and resolve setup, hold, and other timing violations during the design cycle
• Work closely with RTL and Physical Design teams to achieve timing closure
• Develop, review, and manage timing constraints using SDC methodology
• Support timing signoff using industry-standard timing analysis tools
• Debug timing issues across multiple operating corners and modes
• Collaborate with cross-functional teams to ensure timing goals align with design requirements
• Participate in ECO implementation to address timing violations and improve design performance
• Contribute to timing optimization strategies during synthesis and physical design stages
• Maintain documentation and reports related to timing analysis and signoff processes

What Makes You a Great Fit

• 5+ years of experience in Static Timing Analysis for ASIC or SoC designs
• Strong understanding of STA methodologies, timing closure, and signoff processes
• Hands-on experience with industry tools such as Synopsys PrimeTime or Cadence Tempus
• Solid understanding of ASIC/SoC design flows and physical implementation processes
• Experience handling timing constraints, SDC creation, and validation
• Knowledge of ECO flows and timing optimization techniques
• Familiarity with advanced semiconductor technology nodes such as 28nm, 16nm, 7nm, or 5nm
• Strong analytical and debugging skills to identify and resolve complex timing violations
• Ability to collaborate effectively with RTL, synthesis, and physical design teams
• Excellent problem-solving and communication skills within cross-functional engineering environments

Skills

• Static Timing Analysis (STA)