Staff Analog Layout Engineer

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). As a RF layout engineer, you will be responsible for:- Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Proven hands-on experience in layout design and methodology development. Block level and module/IP-level layout through full verification flow including extraction, DRC, LVS, ERC and EM/IR checking. Co-work with designers across geographies on block level and module-level floor planning. Layout review for power/ground routing, electromigration, signal path check, differential and IQ matching, and signal coupling. Top-level layout integration and verification. 8+ years of experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (14nm FinFET and below) Knowledgeable in layout techniques for device matching, minimizing parasitic, RF shielding, and high frequency routing. Solid understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions and advanced process effects such as LOD, WPE, etc. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. Knowledge of CADENCE layout tools virtuoso L & XL. Excellent communication skills and able to work with cross-functional teams. Capability to lead other layout engineers for module/IP-level integration. Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Scripting skills in PERL or SKILL are a plus. Candidates with Scripting knowledge will get the highest preferences.