Staff engineer , ASIC Design Verification

Ensure first‑pass silicon success through comprehensive, multi‑dimensional verification coverage, including mixed‑mode verification. Collaborate closely with domain specialists across global sites on core technical and architectural initiatives. Strong expertise in DDR5 and LPDDR6 protocols. Hands‑on experience verifying complex high‑speed DDR PHYs and AMS IPs. Demonstrated track record of building verification test plans, UVM environments, and testbenches from scratch. Strong proficiency in Verilog, System Verilog, UVM methodology. Solid experience in RTL debugging, score boarding, and functional/code coverage analysis. Excellent written and verbal communication skills, with the ability to work effectively in cross‑functional and globally distributed teams. Prior experience leading or technically driving a team of at least three engineers. M.S./M.Tech or B.S./B.E. in Electronics or a related field. Minimum of 7+ years of relevant ASIC verification experience.