Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

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  Timing Convergence Leadership: Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.).
  
  


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  Cross-Functional Coordination: Partner with Architecture to validate timing feasibility, RTL to optimize logic structures, and DFT to streamline test-mode timing.
  
  


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  Left-Shift Strategy: Proactively identify and resolve structural timing issues, congestion, and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution.
  
  


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  Advanced Analysis: Perform complex timing tasks including CPPR/CRPR analysis, NoC (Network-on-Chip) timing, and constraint validation (SDC).
  
  


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  Automation & Agility: Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility.
  
  


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  PPA Optimization: Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations.
  
  

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  Experience: 9 to 14 years of hands-on experience in STA and Timing Closure on advanced process nodes (7nm, 5nm, or below).
  
  


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  Critical Thinking: Proven ability to debug complex timing violations, identify root causes (e.g., data-to-clock skew, crosstalk), and propose architectural or physical solutions.
  
  


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  Technical Mastery: * Expertise in industry-standard sign-off tools (e.g., PrimeTime, Tempus). Preferable Tempus tool.
  
  




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  Deep understanding of Multi-Mode Multi-Corner (MMMC) challenges and Hierarchical vs. Flat timing closure.
  
  


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  Proficiency in SDC/CDC constraints.
  
  




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  Soft Skills: Strong leadership presence with the ability to influence cross-functional teams and drive execution in a fast-paced environment.
  
  


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  Education: B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.