Staff Silcion Design Engineer - AI

Architect, design, and implement complex Verilog RTL for DRAM/NAND memory subsystems and controllers. Drive micro-architecture definition, logic partitioning, and design optimization for area, timing, and power. Perform block-/chip-level simulations, debug, and functional validation. Automate routine tasks using Python, SKILL, Tcl, or internal toolchains. Work with CAD and EDA teams to support in development and customization of CAD tools and flows to accelerate design and verification cycles thorugh effective use of AI and LLM. Integrate design flows with industry tools (e.g., Cadence, Synopsys, Mentor) for synthesis, simulation, linting, constraints management, parasitic estimation, and layout-aware design. Collaborate with AI/ML teams to integrate models for Automated design rule check, auto layouts, timing estimations and debugging/triaging using RCA.