Staff System Validation Engineer (Post Silicon)

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

The Role:

As a RISC-V System Validation Engineer in the CoreIP team, you will provide technical leadership to a small team of engineers and own system validation execution for SiFive CPU products. You will drive FPGA build and release, define and oversee regression workflows, including Linux boot and performance benchmarks, ensure clear and automated status reporting, and lead first-level failure triage. You will serve as the primary point of contact for system validation execution and act as a bridge between design, verification, and system software teams for debug and analysis.

Responsibilities

• Report to the Director of System Validation (Taiwan) and own the end-to-end system validation execution of SiFive CPU products.

• Manage FPGA-based regressions, ensuring that the design remains healthy and all validation flows are reliable.

• Define, implement, and oversee regression workflows, including Linux boot, performance benchmarks, and other automated tests.

• Generate automated status reports and provide actionable insights to stakeholders.

• Collaborate closely with Design, Verification, and System Software teams to debug and analyze failures.

• Mentor and guide team members on debug methodology, FPGA bring-up, and system validation best practices.

Requirements

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.

• 10+ years of experience in system validation, regression management, or hardware accelerator testing (Design Verification, Emulation, FPGA-based).

• Solid understanding of computer architecture, CPUs, DDR, Ethernet, PCIe, and other IP blocks.

• Strong programming experience in SystemVerilog, Python, and familiarity with other languages used in automation and testing.

• Hands-on experience with CI/CD flows, Jenkins, and automated regression frameworks.

• Proficient in using Git-based version control systems

• Experience with robot-tester frameworks, Jira reporting, and tracking defect lifecycle.

• Strong analytical, problem-solving, and leadership skills, with the ability to guide a small team and collaborate cross-functionally.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.