STA/Timing Engineer

• Responsibilities
  • Strong design understanding with focus on all timing closure aspects
  • Develop timing constraints and provide constraints support for PD STA and interface timing closure.
  • Review timing with cross functional teams, provide feedback and sign-off.
  • Critical path review and on-die uncertainty evaluations.
  • Provide support to SoC integration and chip level pre/post-silicon debug.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

• Skills & Experience
  • MTech/BTech in EE/CS with hardware engineering experience of 2-6 years.
  • Experience in timing closure and debug of complex IP
  • Strong exposure to PT/Tempus flows, scripting (TCL, Perl/Python)
  • Able to work with teams across the globe and possess good communication skills.