Subsystem & Protocol DV Lead

About the company:

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.

Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture.

Anthriq Silicon is our ground-up effort to build a new compute category.

Key responsibilities

• Architect UVM testbenches for memory-subsystem wrappers, credit-based flow control, and multi-channel DMA.


• Develop packet-level protocol checkers, retry-buffer FSM monitors, and error-injection benches for a custom die-to-die link
  layer, incl. cross-die fail-stop.


• Verify hardware synchronization barriers and multi-client arbitration scoreboards.


• Own test-plan execution, mentor junior engineers, drive block coverage to 100%.

Must-have skills

• 8+ years verifying memory controllers (LPDDR4/5/5X) or high-speed interconnect protocols and DMA engines.


• Credit-based flow control, arbitration, memory-map region protection.


• UVM architecture, constrained-random stimulus, functional-coverage modeling.


• Link-layer packetization, retry, framing FSM verification.


• Clock-Domain-Crossing (CDC) verification.

Nice-to-have

• Multi-die / die-to-die (UCIe-class or proprietary) link experience.


• PHY-to-MAC protocol simulation.

Target EDA tools: Cadence Xcelium, vManager, Indago