Verification CAD Engineer, Sr Staff

## \nCompany:\n\nQualcomm India Private Limited\n\n## Job Area:\n\nEngineering Group, Engineering Group \u003e Hardware Engineering\n\nGeneral Summary:\n\nAbout the Role\n\nWe are looking for a highly experienced and technically driven Sr. Staff Verification CAD Engineer to join our Global SoC CAD (GCAD) team. In this role, you will be a methodology leader and technical anchor for Design Verification (DV) CAD, responsible for driving next-generation verification methodologies, UVM-based testbench infrastructure, and cutting-edge Agentic AI solutions for DV automation. You will work closely with DV engineers, IP teams, and AI/GenAI platform teams to shape the future of verification at scale.\n\nKey Responsibilities\n\nDV Methodology Leadership\n\n\u00b7 Define, develop, and drive DV methodologies across IP and SoC verification flows\n\n\u00b7 Own and evolve the UVM-based testbench architecture standards, guidelines, and best practices across multiple design teams\n\n\u00b7 Lead verification planning \u2014 test plans, checker plans, and coverage closure strategies from specification to sign-off\n\n\u00b7 Drive regression infrastructure improvements including debug automation, triage flows, and coverage analysis\n\nAgentic Solutions in DV\n\n\u00b7 Architect and deploy Agentic AI workflows for DV use cases including:\n\n\u00b7 Spec \u2192 Testplan generation\n\n\u00b7 Checker Plan \u2192 SVA/SV-UVM code generation\n\n\u00b7 Regression debug and failure triage agents\n\n\u00b7 Stimulus generation using AI-assisted PSS/UVM flows\n\n\u00b7 Evaluate and deploy external GenAI tools (e.g., Synopsys.ai, Cadence JedAI/Verisium) for DV productivity\n\n\u00b7 Drive dataset creation for DV-specific fine-tuning of LLMs (assertions, drivers, monitors, coverage models)\n\nCAD Tool \u0026 Flow Development\n\n\u00b7 Develop and maintain CAD tools and automation scripts supporting DV flows (Python, Perl, TCL, SystemVerilog)\n\n\u00b7 Enable and support Verification Compiler (VC), simulation tools (VCS, Xcelium), and formal tools (JasperGold, VC Formal)\n\n\u00b7 Drive emulation/prototyping CAD enablement (Palladium, Veloce) for pre-silicon validation acceleration\n\n\u00b7 Contribute to IPQA (IP Quality Assurance) flows and DV sign-off checklists\n\nCross-Functional Collaboration \u0026 Leadership\n\n\u00b7 Serve as a technical mentor and guide for Staff and Senior DV CAD engineers\n\n\u00b7 Partner with DV horizontals, IP teams, and SoC DV teams to align on methodology and tooling\n\n\u00b7 Represent the DV CAD team in program reviews, ops reviews, and cross-site technical forums\n\n\u00b7 Drive efficiency KPIs \u2014 regression TAT, coverage closure rate, bug escape metrics\n\nMinimum Qualifications:\n\n\u2022 Bachelor\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. \nOR \nMaster\u0027s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. \nOR \nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nRequired Qualifications\n\nArea Requirements\n\nEducation B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering\n\nExperience 12+ years in Design Verification / Verification CAD\n\nDV Expertise, Deep expertise in SV-UVM testbench development, constrained random verification, functional coverage, SVA Scripting \u0026 Automation, Strong proficiency in Python, Perl, TCL, Makefile-based flows\n\nAgentic/GenAI Experience or strong interest in LLM-based code generation, agentic workflows, RAG systems for DV\n\nTools: VCS / Xcelium, Verdi / DVE, Palladium/Veloce (preferred)\n\nMethodology: Verification planning, coverage-driven verification, low-power verification, DFT verification\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm\u0027s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. 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Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.\n