Senior Digital Verification engineer

LA NOSTRA STORIA\n\nNoi di ST crediamo nel potere della tecnologia di guidare l\u2019innovazione e avere un impatto positivo sulle persone, sulle imprese e sulla societ\u00e0. Siamo un\u0027azienda globale di semiconduttori e la nostra tecnologia avanzata e i nostri chip costituiscono la parte nascosta del mondo in cui viviamo oggi.\n\nEntrando in ST farai parte di un\u0027azienda di oltre 115 nazionalit\u00e0 e presente in 40 paesi, con oltre 50.000 creatori di tecnologia in tutto il mondo!\n\nLo sviluppo di tecnologie richiede pi\u00f9 del solo talento: siamo infatti alla ricerca di persone straordinarie che comprendano la collaborazione e il rispetto. Persone con passione e il desiderio di rompere lo status quo, guidare l\u0027innovazione e sbloccare il proprio potenziale. Intraprendi un viaggio con noi, dove puoi innovare per un futuro che vogliamo rendere pi\u00f9 intelligente e pi\u00f9 verde, in modo responsabile e sostenibile. La nostra tecnologia inizia con te..\n\nRole\n\nWe are looking for a Digital Verification Engineer \u2013 SoC to join our MDRF-RFOC-DVCC Digital Verification team in Naples, dedicated to the digital verification of complex SoC/IP for automotive / industrial applications.\n\nThe selected candidate will work on SystemVerilog UVM testbenches, firmware / drivers in C, and Python scripts for automation, contributing to the entire verification cycle: from strategy definition to environment creation, up to coverage analysis and debug. \nWithin the team we also use AI-assisted tools and methodologies to accelerate development, debug, and results analysis, and we expect the candidate to be curious and interested in leveraging these technologies in day-to-day activities.\n\nMain Responsibilities\n\n * Define, in collaboration with architects and designers, the verification strategy at IP and/or SoC level.\n * Develop and maintain UVM testbenches in SystemVerilog (environment, agent, sequencer, driver, monitor, scoreboard).\n * Write and integrate C tests for subsystem and SoC verification in simulation and/or emulation environments.\n * Develop Python scripts (and, when needed, bash/Tcl/Perl) for:\n * regression automation,\n * post-processing of results,\n * coverage analysis and report generation.\n * Perform functional debug of failing test cases, interacting with the design (RTL) team and system architects.\n * Run and debug gate-level simulations with SDF back-annotation, analyzing timing-related issues and collaborating with design and implementation teams to identify and resolve problems.\n * Analyze and manage functional coverage and code coverage, proposing new tests or testbench improvements to meet quality targets.\n * Use AI-assisted tools and workflows for:\n * generation and review of testbench code and scripts,\n * log analysis,\n * debug acceleration.\n * Contribute to the continuous improvement of verification flows (methodologies, common libraries, guidelines, best practices).\n * Produce clear and structured documentation for:\n * verification specifications,\n * testbench architecture,\n * test plans,\n * key results.\n\n\n\nTechnical Requirements Mandatory (must-have)\n\n * Degree in Electronic Engineering, Computer Engineering/Science, Physics with an electronics focus, or related disciplines.\n * Solid knowledge of digital verification of integrated circuits (RTL concepts, testbench, stimuli, checkers, coverage).\n * Hands-on experience with SystemVerilog and UVM methodology:\n * development of UVM components (sequencer, driver, monitor, scoreboard),\n * environment configuration,\n * sequence and virtual sequence management.\n * Good command of the C language for verification-oriented test/firmware driver development.\n * Experience with Python for scripting and automation.\n * Good knowledge and practical use of the Unix/Linux environment (shell, file system, batch jobs, compilation, basic scripting).\n * Familiarity with major digital simulators (e.g. Cadence Xcelium, Synopsys VCS, Siemens Questa).\n * Basic knowledge of version control flows (Git, SVN, DesignSync).\n * Good command of written and spoken English.\n * 5-8 years of experience in the role\n\n\n\nDesirable (nice-to-have)\n\n * Experience with SoC/IP verification (AMBA/AXI/APB/AHB buses, memory interfaces, peripherals, interrupt controllers, DMA, etc.).\n * Basic knowledge of machine learning / AI and use of AI tools for:\n * code generation,\n * log analysis,\n * test and scenario creation.\n * Knowledge of formal verification techniques (e.g. property checking, assertion-based verification) and familiarity with formal tools.\n * Experience in ISO 26262 environments.\n * Knowledge of other scripting languages (bash, Tcl, Perl) and related EDA tools (lint, CDC, STA) is a plus.\n\n\n\nPersonal Skills\n\n * Analytical mindset and strong problem-solving attitude.\n * Attention to detail and strong product quality orientation.\n * Ability to work in cross-functional teams (design, architecture, emulation, firmware).\n * Proactivity in proposing flow improvements and automation.\n * Willingness to learn new technologies, particularly AI tools and methodologies applied to engineering.\n * Good communication and technical documentation skills.\n\n\n\nST \u00e8 orgogliosa di essere una delle 17 aziende certificate come Top Employer Globale 2025 e la prima e unica azienda di semiconduttori a raggiungere questa distinzione. ST \u00e8 stata riconosciuta in questa classifica grazie al suo approccio di miglioramento continuo e si distingue particolarmente nelle aree di etica e integrit\u00e0, scopo e valori, organizzazione e cambiamento, strategia aziendale e performance.\n\n \n\nIn ST, ci impegniamo a promuovere un ambiente di lavoro diversificato e inclusivo, e abbiamo tolleranza zero per la discriminazione. Miriamo a reclutare e mantenere una forza lavoro diversificata che rifletta le societ\u00e0 intorno a noi. Ci sforziamo per l\u0027equit\u00e0 nello sviluppo della carriera, nelle opportunit\u00e0 di carriera e nella remunerazione equa. Incoraggiamo i candidati che potrebbero non soddisfare tutti i requisiti a presentare domanda, poich\u00e9 apprezziamo le prospettive diverse e offriamo opportunit\u00e0 di crescita e apprendimento. La diversit\u00e0, l\u0027equit\u00e0 e l\u0027inclusione (DEI) sono intrecciate nella nostra cultura aziendale. La nostra visione DEI \u00e8: \"In ST, puoi essere la versione autentica di te stesso\".\n\n \n\n\n \n\n\nPer saperne di pi\u00f9 visita il sito: st.com/careers\n