Analog Layout Student

The business line APN develops highly integrated solutions for the automotive industry. The Layout engineering team based in Milan is delivering SoC layouts to multiple product lines addressing the automotive and industrial applications.

We are looking for an IC Analog Layout Student to work with our product organizations to define and develop the next generation of SoC.

The candidate will be part of the team and deliver major contributions at both top and block level of the products.

As a member of the team, you will be responsible for:

• Delivering floorplan activities at IP level.
• Participating to the power supply strategy, signals distribution of blocks.
• Delivering Analog layout blocks.
• Running all physical verifications such as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries.
• Participating to design reviews, write documentation and support for integration into products.
• Having a strong focus on design for quality (designs are properly verified, validated, and tested for long-term reliability and zero defect).

Your Profile

• Fluent in Italian and in English
• Ability to collaborate with experienced people having different technical profiles.
• Engaged, committed
• Curious, agility to learn
• Excellent capability to communicate and synthesize, Collaborative

Required profile characteristics

• Fluent in Italian and in English
• Ability to collaborate with experienced people having different technical profiles.
• Engaged, committed
• Curious, agility to learn
• Excellent capability to communicate and synthesize, Collaborative

Furthermore, following skills are a plus:

• Knowledge in Analog layouts.
• Knowledge in layout design tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre).
• Knowledge in physical implementation in Analog blocks at IPs and/or SOC level.

More information about NXP in Italy...