Thesis Internship Digital IP Designer

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo,  drive innovation, and unlock their own potential. 

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

General Purpose & Automotive Microcontroller (GPAM) division is developing Networking Digital IPs for Microcontroller products in leading edge technologies requiring state of the art architecture.

In an Ethernet network for industrial and automotive applications, specific profiles and related standards are required.  To ensure proper QoS for scheduled traffic, specific hardware support for related protocols is mandatory. Furthermore, faulty or malicious data streams can propagate, preventing the timely reception of other critical control traffic. This is unacceptable for in-vehicle networks, where Ethernet is the primary in-vehicle network technology enabling the implementation of advanced driver assistance systems. For this reason, hardware protocol support is mandatory to meet bandwidth, latency, and security requirements.

YOUR ACTIVITY

• Studying of the IEEE 802.1AE standard


• Designing the micro-architecture of a sub-block which will be integrated inside a multi-layer switch IP.​


• Describing the sub-block micro-architecture in System Verilog.​


• Stand-alone test of the developed sub-block.​


• Integration and testing (UVM-based) of the developed sub-block inside the final IP. ​


• RTL signoff and synthesis trials will be also performed during the thesis period.​


• FPGA validation tests is a plus (recommended)​

YOUR SKILLS & EXPERIENCES

• Graduated in Electronic Engineering, sciences or similar


• Skilled in HW Design - Embedded System – RTL Coding


• Language Knowledge: Python VHDL - Verilog - System Verilog / C – C++ – UNIX 


• Appreciated Knowledge of Objective Oriented programming


• Strong Teamwork spirit and Communication skill


• Proactive and problem-solving attitude


• English proficiency

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture. 

To discover more, visit st.com/careers.