Layout Design Technical Manager

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Layout Design Technical Manager

Apply locations Malaysia, Penang time type Full time posted on Posted Yesterday job requisition id JR0262673

Job Details:

Job Description: 

Directs and guides the activities of mask designers and/or layout engineers and their functions, activities, and responsibilities. Oversees designing, developing, modifying, analyzing, and verifying chip level layouts and floorplans. Provides guidance for analog design, digital design, memory design, and standard cell layout methodologies, compilers, tools, and flows. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.This technical managerial role requires the individual with Layout design and LV flows, scripting expertise is a plus, and a strong passion to mentor and develop the team to deliver world class result.In this managerial role, responsibilities include although not limited to:Manage a team of engineers responsible for above mentioned tasks.Plan, allocate resources, assign tasks and direct activities of the team to meet aggressive schedules and achieve milestone criteria.Identify and analyze progress gating issues and implement plans, tasks, and solutions to quickly resolve.Propose creative, innovative methodology and process initiatives to consistently improve efficiency and quality of deliverables.Provide coaching, guidance and feedback to direct reports on career development, performance, and productivity issues.Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.#designenablement

Qualifications:

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Bachelor degree (Master degree preferred) in Electrical Engineering, Computer Engineering or a related discipline with 2+ years experience OR PhD in Electrical Engineering, Computer Engineering or a related discipline.Experience in the following:Memory layout design and verificationPreferred Qualifications:custom memory (SRAM, Register File, ROM) layoutMemory Layout Floorplan and verificationLayout AutomationInside this Business GroupAs the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.#designenablement

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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