A

Design Verification Engineer

icon briefcase Jenis Pekerjaan : Sepenuh Masa

Bilangan Pemohon

 : 

000+

Click to reveal the number of candidates who applied for this job.
icon loader
Mohon Sekarang
icon loader Mohon Sekarang

Let AI Supercharge Your Job Hunt!

JobCopilot scans 500,000+ company career sites daily to find jobs for you

Never miss an opportunity Save hours by auto-filling applications forms Land more interviews with tailored applications
happy man
thunder iconActivate JobCopilot

Penerangan Pekerjaan - Design Verification Engineer

Job Details:

Job Description:

  • Performs functional logic verification of an FPGA to ensure design will meet specification requirements.

  • Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.

  • Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.

  • Replicates, root causes, and debugs issues in the pre-silicon environment.

  • Finds and implements corrective measures to resolve failing tests.

  • Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

  • May also collaborate with systems and software engineers to support integration testing of the FPGA.

  • Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.

  • Maintains and improves existing functional verification infrastructure and methodology.

  • Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Qualifications:

  • BS, MS or PhD in Electrical or Computer Science Engineering or related field with 3+ years of technical experience.

  • Related technical experience should be in/with: Pre Silicon Validation/Verification.

  • OVM/UVM, System Verilog, constrained random verification methodologies.

  • Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.

  • Able to handle verification life cycle (verification architecture, test plan, execution, debug, coverage closure).

  • Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.

  • Experience in FPGA architecture or FPGA prototyping

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Original job Design Verification Engineer posted on GrabJobs ©. To flag any issues with this job please use the Report Job button on GrabJobs.
Mohon Sekarang
Share Job
Share Job

Auto-Apply to Design Verification Engineer Jobs with your AI JobCopilot

thunder icon Auto-Apply with AI

Similar Design Verification Engineer Jobs in Malaysia

GrabJobs ialah portal pekerjaan no1 di Malaysia, menghubungkan anda dengan beribu-ribu pekerjaan dengan pantas! Cari kerja terbaik di Malaysia, mohon dalam 1 klik dan dapatkan pekerjaan hari ini!

Aplikasi Mudah Alih

Copyright © 2026 Grabjobs Pte.Ltd. All Rights Reserved.