DFT Engineer

• Work with front -end team, DFT, and cross -functional teams to provide the solutions and make sure DFT DRCs are fixed
  
• Generating high -quality manufacturing ATPG test patterns for (SAF) stuck -at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on -chip test compression techniques.
  

Requirements

• BE/ BTech/ MTech/MS/ PhD in Electronics, Electrical, Computer Engineering or Computer Science Engineering with 4 - 10 years of exp.
  
• Highly motivated and driven to face challenging design and debug problems
  
• In -depth knowledge and hands -on experience in scan insertion, ATPG, coverage analysis, and Transition delay test coverage analysis.
  
• Analyze the design and propose the best compression technique.
  
• In -depth knowledge and hands -on experience in Scan insertion and validation, BIST, LBIST, MBIST insertion and verification, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis, and sign -off.
  
• Hands -on experience in various DFT aspects like Scan insertion, MBIST and Boundary Scan, ATPG, Pattern validation at block level as well as Full -chip level
  
• Tessent DFT expertise – methodology and flow development
  
• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is desired.
  
• Scripting Languages – Shell scripting, Python, TCL, PERL etc.
  
• Be able to work and support Test Engineers for post -silicon tasks.