Lead Analog IC Layout Engineer

Seeking an experienced Analog Layout Engineer with a Bachelor's Degree in Electrical / Electronic Engineering or Physics, to lead and execute IP/full-chip layout from planning to verification, ensuring high-quality and on-time delivery.

Key Responsibilities:

• Lead or co-lead IP/full-chip layout activities from scratch.

• Perform floor planning, routing, and layout verification (LVS, DRC, Antenna checks).

• Collaborate with cross-functional teams for seamless layout integration.

• Conduct internal and external layout design reviews.

• Utilize CAD tools (Cadence Virtuoso VXL, Mentor Calibre) for layout and checks.

• Troubleshoot layout issues and resolve violations efficiently.

• Mentor and guide junior engineers to ensure quality and delivery.

• Drive layout optimization and methodology improvement.

Required Skills:

• 9 - 14 years of experience in analog layout with VLSI exposure.

• Proficient in submicron CMOS layout techniques.

• Strong knowledge of IR drop and EM analysis.

• Hands-on with Cadence Virtuoso and Mentor Calibre.

• Excellent problem-solving and analytical abilities.

• Effective communicator with initiative and teamwork skills.

• Experience in analog layout from scratch.

• Capable of working across functions and teams.