Lead and own the physical design flow from RTL - GDSII for complex sub -systems consisting of several blocks.
Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing and signoff (timing, IR, EM, DRC/LVS)
Handle sub -system level PD and provide necessary feedback to full -chip owner.
Coordinate with block -level PD owners and ensure seamless integration at sub -system level.
Analyze and optimize PPA (Power, Performance, Area) to meet design targets.
Collaborate with RTL, STA, power DFT and verification for design convergence.
Lead ECO cycles for timing, congestion and physical signoff closure.
Review and debug physical verification and timing issues.
Manage schedules, resources and risk tracking for PD deliverables.
Prepare and present project status, risk and mitigation plans to management and customer.
Mentor and guide junior engineers in the team.
Requirements
Required Skills and Experience:
10+ years of experience in ASIC/SOC Physical Design with at least 1+ years in a lead role
Strong expertise in industry standard PD tools (Innovus, Tempus, Voltus, RedHawk, Calibre)
Proven experience in sub -system level integration and signoff flows.
Good understanding of STA, Physical Verification and low -power design methodologies (UPF/CPF)
Hands on experience with lower process nodes (16nm and below preferred)
Strong debugging and problem solving skills in timing, congestion and physical verification
Hands on experience in handling Analog custom routes, understanding specification to meet R and C
Experience in multi -voltage, multi -frequency design
Knowledge of EM/IR -drop analysis and mitigation
Excellent communication and leadership skills
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