Lead and own the physical design flow from RTL - GDSII for complex blocks.
Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing and signoff (timing, IR, EM, DRC/LVS)
Handle complex blocks including multiple blocks if required.
Interact with sub -system leads and full -chip owner to provide necessary feedback.
Analyze and optimize PPA (Power, Performance, Area) to meet design targets.
Collaborate with RTL, STA, power DFT and verification for design convergence.
Lead ECO cycles for timing, congestion and physical signoff closure.
Review and debug physical verification and timing issues.
Manage schedules, and risk tracking for PD deliverables.
Prepare and present project status, risk and mitigation plans to sub -system leads and customer.
Work effectively with large teams consisting of multiple vendors.
Requirements
Required Skills and Experience:
6 -9 years of experience in ASIC/SOC Physical Design handling complex blocks.
Strong expertise in industry standard PD tools (Innovus, Tempus, Voltus, RedHawk, Calibre)
Proven experience in block closure and signoff flows.
Good understanding of STA, Physical Verification and low -power design methodologies (UPF/CPF)
Hands on experience with lower process nodes (16nm and below preferred)
Strong debugging and problem solving skills in timing, congestion and physical verification
Hands on experience in handling Analog custom routes, understanding specification to meet R and C
Experience in multi -voltage, multi -frequency design
Knowledge of EM/IR -drop analysis and mitigation
Excellent communication and leadership skills
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