Requirements
Responsibilities:
Lead and own the Full -Chip physical design flow from RTL - GDSII
Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing and signoff (timing, IR, EM, DRC/LVS)
Handle chip -level bump planning, clock planning, time budgeting and analog custom routing. Interact with package team.
Coordinate with sub -system level PD owners and ensure seamless integration at chip -level.
Analyze and optimize PPA (Power, Performance, Area) to meet design targets.
Collaborate with RTL, STA, power DFT, verification and package teams for design convergence.
Lead ECO cycles for timing, congestion and physical signoff closure.
Review and debug physical verification and timing issues.
Manage schedules, resources and risk tracking for PD deliverables.
Prepare and present project status, risk and mitigation plans to management and customer.
Mentor and guide junior engineers in the team.
Required Skills and Experience:
12+ years of experience in ASIC/SOC physical design with at least 2+ years in a lead role
Strong expertise in industry standard PD tools (Innovus, Tempus, Voltus, RedHawk, Calibre)
Proven experience in full -chip integration and signoff flows.
Good understanding of STA, Physical Verification and low -power design methodologies (UPF/CPF)
Hands on experience with lower process nodes (16nm and below preferred)
Strong debugging and problem solving skills in timing, congestion and physical verification
Familiarity with package/chip co -design and IO planning.
Hands on experience in handling Analog custom routes, understanding specification to meet R and C
Good hands on experience in Full -Chip CTS implementation
Good hands on experience in IO bump planning, Partitioning, Time Budgeting VA creation (Design Planning activities)
Experience in multi -voltage, multi -frequency design
Knowledge of EM/IR -drop analysis and mitigation
Excellent communication and leadership skills
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