Physical Design - STA Lead

Syarikat : Signoff Semiconductors

Jenis Pekerjaan : Sepenuh Masa

Bayan Lepas, Malaysia

Penerangan Pekerjaan - Physical Design - STA Lead

Requirements

Oversee full -chip and/or sub -system level STA convergence from early stages to signoff.

Take part in top -level floorplan and clock planning.

Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime.

Manage schedules, resources and risk tracking for STA deliverables.

Prepare and present project status, risk and mitigation plans to management and customer.

Mentor and guide junior engineers in the team.

Required Skills and Experience:

10+ years of experience in ASIC/SOC STA with at least 1+ years in a lead role.
Strong experience in ASIC timing constraints generation, validation and timing closure.

Expertise in Tempus/Primetime and timing eco (physical aware) using Tempus ECO/PT -DMSA/Tweaker - full -chip and sub -system level.

Experience in IO Timing/interface budgeting/process margins/corner definitions

Familiarity with DFT.

Proficient in scripting language (TCL/python).

Excellent timing and flow debugging skills.

Experience in ECO generation flow for RTL, pre -physical and post route implementation considering timing, congestion and logic equivalence.

Automation to improve PPA (power/performance/area) and ensure a high -quality design environment for SOC.

Proficient in scripting language (TCL/python).

Hands on experience in reference flows, excellent debugging skills.

Alamat E-mel

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Aplikasi Mudah Alih

Dasar Privasi Syarat Penggunaan

Physical Design - STA Lead

Penerangan Pekerjaan - Physical Design - STA Lead

Requirements

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Aplikasi Mudah Alih