Senior Soft IP Design Engineer

Responsibilities:

• The Employee should be a passionate individual with technical leadership

• capabilities to build Connectivity IP portfolios for Lattice FPGA. The

• Employee should have the ability to work closely with architect to

• translate specifications into high-speed RTL design, for the best

• Performance, Power and logic utilization.

Qualifications:

• BS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of FPGA IP design experience.

• Independent and self-motivated, capable of executing under dynamic environment and uncertainties.

• Experience in high speed SERDES protocols (e.g.: PCIe, Ethernet, CPRI or JESD204B/C) or Memory (DDR4, LPDDR4, etc) is a plus.

• Hands-on experience in FPGA RTL design, logic verification, debug and timing closure is preferred.

• Programming skills (e.g.: C/C++, Perl, TCL or Python).

• Experience in hardware validation or hardware interoperability test is a plus.

• Experience in soft IP packaging, example design and testbench development will be an added advantage.