Serdes Digital Design Architect

Syarikat : Uni Connect

Jenis Pekerjaan : Sepenuh Masa

Penang, 10200

Penerangan Pekerjaan - Serdes Digital Design Architect

We are looking for a veteran digital architect who can own and drive the digital subsystems of our next-generation 112 Gb/s-and-beyond Ethernet SerDes.
This role collaborates closely with analog, DSP, firmware, and SoC teams, translating high-level requirements into clean RTL that meets power, performance, and area (PPA) targets—and also guide the design through synthesis, STA, and physical implementation.

Key Responsibilities:
· Define and document the digital micro-architecture for PMA/PMD/PCS blocks, including DSP datapaths and control processors.
-Write high-quality Verilog RTL, verify it (directed + UVM), and debug corner cases across multiple asynchronous clock domains.
· Collaborate daily with analog designers to understand and model mixed-signal effects, ensuring robust digital-on-top flows.
· Craft timing constraints, run STA, and close timing in cutting-edge FinFET nodes.
· Drive lint/CDC/RDC clean-up and formal checks.
· Explore FPGA/prototype platforms to validate algorithms and bring-up firmware pre-silicon.
· Contribute to embedded microcontroller firmware for calibration, adaptation, and link-training routines.

Requirements

Requirements:
· Master's degree or higher in Electrical Engineering
· 10+ years of hands-on experience architecting and implementing high-speed (>32 Gb/s) SerDes or similar high-performance mixed-signal IPs.
· Deep expertise in Verilog/SystemVerilog, synthesis, and STA; familiarity with physical design flows (floor-planning, CTS, routing, IR-drop, EM).
· Proven ability to balance PPA trade-offs and to communicate them clearly to both analog and digital peers.
· Solid grasp of DSP concepts and algorithms (FFE, DFE, CTLE, FEC).
· Working knowledge of the Ethernet protocol stack (IEEE 802.3bs/cd/cg) and PMA/PMD/PCS layer requirements.
· Comfortable with multi-clock-domain design, CDC strategies, and industry-standard verification tools.
· Self-starter who can triage issues across RTL, gate-level netlists, and lab silicon.
• Bonus points for:
– FPGA/emulation bring-up experience.
– Embedded C/Firmware development for RISC-V or proprietary microcontrollers.
– Exposure to advanced process nodes (7 nm, 5 nm, 3 nm)

Original job Serdes Digital Design Architect posted on GrabJobs ©. To flag any issues with this job please use the Report Job button on GrabJobs.

Share Job

Get your Resume Reviewed for Free

Mengenai Syarikat

Uni Connect

Looking for the Top Semiconductor and AI Acquisition Firm in Singapore? UniConnect is your trusted job agency for recruitment solutions in Singapore.

Baca lebih lanjut mengenai syarikat

Similar Digital Design Architect Jobs in Malaysia

Get your Resume Reviewed for Free

Alamat E-mel

Mengapa anda melaporkan kerja ini?

I think it’s a discriminatory or offensive

I think it’s fraudulent or a scam

I think it’s trying to sell something unrelated to the job / it’s asking for money

I think it contains incorrect or broken information

Other

Semua Iklan Pekerjaan adalah tertakluk kepada Terms of Service GrabJobs. Kami membenarkan pengguna membenderakan siaran yang mungkin melanggar syarat tersebut. Iklan Pekerjaan juga mungkin dibenderakan oleh pasukan penyederhana GrabJobs. Walau bagaimanapun, tiada sistem penyederhanaan yang sempurna dan membenderakan siaran tidak memastikan bahawa ia akan dialih keluar.

Sediakan makluman pekerjaan:

Kekerapan

E-mel

Dengan mengaktifkan makluman kerja, saya bersetuju menerima GrabJobs Terms & Privacy Policy. Saya boleh berhenti melanggan makluman kerja pada bila-bila masa. Langkau

Serdes Digital Design Architect

Penerangan Pekerjaan - Serdes Digital Design Architect

Requirements

Mengenai Syarikat

Similar Digital Design Architect Jobs in Malaysia

Aplikasi Mudah Alih