Sr Analog Layout Engineer

• Development of innovative analog layout ( floor planning, device placement, matching and
  routing, LVS, DRC, DFM check and reliability verification ) and solving technical issues in
  different process technologies.
  
• Responsible for layout optimization, post layout extraction and parasitic analysis.
  
• Collaborate with Design Lead, Circuit designers, and Layout engineers to implement custom
  IPs and archive full chip integration, place and route, top level verification and tape out.
  
• Deliver quality engineering work that meets and exceeds customer expectations all the time
  
• Guide and coach juniors by ensuring their works meets the desired area, performance and
  power consumption.
  

Requirements

• Minimum 3 years of experience in analog IC layout
  
• This position can be based in Penang or KL.
  
• Technical Expertise: Proficiency in Cadence Virtuoso.
  
• Engineering Depth: Solid understanding of device characteristics, device/signal matching,
  EMIR, and RC effects.
  
• Education: Bachelor’s Degree in Electrical/Electronic Engineering or a related VLSI field.
  
• Collaboration: Strong communication skills with the ability to function effectively within a
  high -caliber design team.
  
• Preferred Skills: Experience in Analog layout or proficiency in automation scripting (SKILL,
  Python, or Perl) is a significant advantage.