SoC Design Engineer

We are hiring SoC Design Engineer (DFT)

Key responsibilities:

• SoC DFT architecture definition and test plan development.
• Perform IP level and top level DFT integration, test insertion and verification.
• DFT rule check to ensure design meet testability requirement and test coverage goal.
• Develop RTL code for DFT logics, including BIST, JTAG TAP and IP test wrapper.
• Test modes timing constraints development and DFT mode timing closure.
• DFT tools flow and test methodology development, including ATPG, test insertion, BIST, diagnostic, low power, High-speed I/O and analog/mixed signal IP testing.
• Develop and verify functional and scan test vectors for ATE.
• Work with test development team on silicon turn-on, IP characterization, test debug and yield improvement activities.

Requirements:

• Bachelor / Master Degree in Electrical & Electronic or equivalent.
• Experience in SoC design/verification with industry tool flows (Synthesis, Scan insertion, ATPG, simulator, LEC, STA).
• Familiar with verilog, system verilog and Perl/Tcl script.
• Knowledge in advance DFT methodology including ATPG, MBIST, JTAG, high-speed interface test and etc.
• ATE test development and post-silicon test debug experience is an added advantages.
• Minimum 5 years relevant working experience for senior position, and 8+ years for staff position.

Dft, Ate, ATPG, Perl, bist , Verilog, SOC design, RTL, System Verilog, Tcl