Senior Digital Design Engineer

Role - Senior Digital Design Engineer
Location - The Netherlands – Enschede / Nijmegen
Salary - 70,000 EUR per annum, plus 20% bonus No visa sponsorship available Role-
The candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Essential Functions -
- Digital Design (RTL design): ASIC or FPGA from concept to implementation
- Digital Verification: Development test plans, test benches and automated test cases
- Knowledge and/or responsibility in synthesis, timing closure, and formal verification.
- Create scripting to support design and verification automation Qualifications -
- PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
- Extensive experience in design plus verification of ASIC or FPGA
- Strong knowledge of ASIC development process and digital design techniques
- Proficient in standard DV languages (Verilog, SystemVerilog, UVM)
- Experience with programming, scripting and automation languages(C/C++, shell, Perl, TCL, Python, etc).
- Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc. If you are interested, Please contact [email protected] and provide your CV.

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