Staff Digital Design Engineer

Role – Staff Digital Design Engineer
Location – The Netherlands, Enschede & Nijmegen
Salary – 75,000 EUR per annum NO VISA SPONSORSHIP AVAILABLE Job summary – The candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. Candidate will be expected to lead designer, verification, and be technical focus on one or more device and/or sections. Candidate will also be expected to support pre/post-silicon design validation and support Design/ATE/Application & Systems group. Essential Functions – Digital Design (RTL design): ASIC or FPGA from concept to implementation
Digital Verification: Development test plans, test benches and automated test cases
Knowledge and/or responsibility in synthesis, timing closure, and formal verification.
Create scripting to support design and verification automation
Estimate and manage time/tasks completion to target schedule Qualifications –-PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
-8+ years’ experience in design plus verification of ASIC or FPGA
-Strong knowledge of ASIC development process and digital design techniques
-Proficient in standard DV languages (Verilog, SystemVerilog, UVM)
-Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc
-Experience with programming, scripting and automation languages(C/C++, shell, Perl, TCL, Python, etc).
-Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc. If you are interested, please contact; [email protected] and provide your CV.

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