Front End Digital IC Design Engineer (Senior / Staff) - Room for Advancement

Front-End IC Design Engineer (Senior / Staff)

Work location: Singapore

Work Arrangement: Hybrid

Job Description：

1. Responsible for digital part design on millimeter wave radar chips, including SOC architecture discussion, chip spec discussion, SoC integration and IP design;

2. RTL design & coding, RTL and gate-level simulation & verification, synthesis and STA；

3. Chip performance and power consumption assessment;

4. LINT and CDC check;

5. Debug work on FPGA platform

6. Work closely with analog designers, DFT designer, APR engineer and firmware engineers for smooth production

Must have requirement:

Min of 4-5 years of Verilog RTL design (at module level) work experience

Job Requirements：

1. Bachelor or Master’s degree in electronic engineering, at least 4 years’ experience in RTL design & coding, simulation, synthesis and STA

2. Experience in LINT and CDC check;

3. Good understanding of DFT;

4. Experience in CSI and SPI design would be a good plus;

5. Experience in DSP design would be a good plus;

6. Good communication and interpersonal skills, a good team player;

We invite you to write in to Kevin at [email protected] , with your updated CV (in MSWord format). We regret to inform only selected candidates will be notified. However, if you are not selected, we will keep your CV and contact you for suitable role(s) that comes along.

Kevin Chong

WA: +65-62957159

EA Reg No. R1109670

EA License No. 22S1412