ASIC Design Engineer (RTL)

• Responsible for RTL design, simulation, and verification for ASIC/SoC products.
• Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team.
• Create reusable internal IPs for AI and/or in-memory computing products.
• Handle IP integration and validation and support post-Si testing and validation.

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Requirements:

• Degree in Electrical Engineering or equivalent
• At least 5 years of RTL/SoC/digital design with pre-layout simulation and post-layout simulation experience.
• Strong knowledge with Verilog and system Verilog, VCS, Verdi or other industry standard tools.
• Familiarity with AMBA APB AXI Protocol, RISC/Arm or other core architectures.

If you are keen to apply for the position, kindly email your detailed resume in MS Word to [email protected]

Please note that only shortlisted candidates will be notified.

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EA Licence: 19C9701

Registration: R1326740