Engineering Manager - Silicon Design

Deep expertise in ASIC IP/ASIC SoC design, Verilog, and System Verilog. Proficiency in front-end tools (Verilog simulators, linters, clock domain crossing checkers) Familiarity with synthesis, static timing analysis, DFT. Knowledge of System-Verilog assertions, checkers, and additional design verification techniques are advantageous. Familiarity in scripting languages like Python etc. Extensive understanding of modern silicon design techniques. Experience in leading, coordinating and supporting geographically dispersed engineering teams. Master of Science, Electrical Engineering, Computer Science, Physics or similar with 10+ years of experience Self-driven with the ability to manage high engineering support loads across multiple teams located in Stockholm and Lund ​What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop. Please apply with your cover letters. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. learn more. Primary country and city: [[Sweden]] || [[Stockholm]] Primary Recruiter: [[Anitha Pulluru]] Hiring Manager: [[Edward Lindenholst]]