PhD in Development of a wireless RF link on FPGA and associated security tools

Context

Today's systems are more and more interconnected. Since the advent of the Internet of Things (IoT), any sensor can be interfaced with a local network or the Internet. This massive

deployment has created many security issues and associated solutions. The security of the

communication can be done thanks to cryptography. However, the complexity of the solution does not necessarily make it compatible with very low-cost systems such as can be found in a sensor network. Another security flaw studied concerns hardware attacks. Indeed, covert channel analysis, such as power supply analysis, or fault injection attacks, such as sending electromagnetic pulses, can copy the operation of a device in order to add a third-party object in the network or to make it inoperative. These attacks can also disrupt the generation of data encryption keys by attacking the chip's random number generator. To avoid them, it is possible to shield the chips to avoid any radiation or to use error correcting codes. However, solutions are often cumbersome to implement in an IoT device.

Thesis objectives

The thesis will be part of a European project on the creation of a secure chip for IoT systems. The main objective of the thesis is to design a low speed wireless link without using any analog component and to associate tools to identify an IoT module and to detect hardware attacks in real time during the communication. During the project, these modules will be emulated by RF FPGA boards designed at the beginning of the project. The first objective of the project will therefore be to propose a very low cost wireless link without analog components using simple digital modulation in the ISM frequency bands by simply adding an antenna to the FPGA component. During a previous work, our team showed that it was possible to use FPGA components at RF frequencies (around 600 MHz) to perform OOK (On-Off Keying) wireless links over several meters using an amplifier. The innovation of this first objective lies in the possibility of operating in ISM bands without any analog components (saving space, cost, consumption). A particular work on the FPGA such as the study of the ring oscillators (RO) used for the carrier will be carried out in order to allow a frequency rise. The link will then be fully characterized in terms of throughput, range and bit error rate. The second objective is to add functionalities to identify a network module and to detect hardware attacks on it using the developed wireless link. Indeed, the communication carrier signals are generated by ROs. This type of resonator, used in particular in random number generators, have the particularity of being very sensitive to the characteristics of the chip: threshold voltage, supply voltage, temperatures, etc. Two identical resonators implemented in two different places in an FPGA will therefore have a slightly different frequency. This property has been used to authenticate FPGAs in the Protect project. By using these ROs to communicate, whose frequency will be specific to the device, it is possible to define an identifier associated with its frequency. It will also be possible to detect an attack by monitoring the frequency variations of the oscillators at the reception because they are very sensitive to any variation of the environment. The monitoring module will be developed at the logic level, as close as possible to the hardware. The more we work at low level, the more we will have a fine control on the system. We will work on the number of resonators per module to make the identification and monitoring as reliable as possible.

Qualification

The candidate should possess an M.Sc./M.Eng. Degree in Telecommunication, digital design

Engineering, or a closely related field in Electronic and Electrical.

Experience

The ideal candidate should have a strong background in digital communications, digital system design substantiated by relevant coursework/assignments. The candidate must be

comfortable with digital system design on FPGA using VHDL/verilog. In addition, a background and interest in a number of the following areas is required: Wireless communications, Digital signal processing, RF and microwave engineering. Hands-on experience with RF electronics is a plus.