Digital Verification Engineer

Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre), India (Bangalore) and Hungary (Budapest). EnSilica currently employs more than 200 people.

We are looking for a bright engineer with a passion for silicon engineering and the ambition to invest your energy on a semiconductor career path. You will have a strong academic record and already a 2+ years’ experience in IC verification where you will have demonstrated excellent problem solving skills and the ability to work in a team in a dynamic environment.

You will be already knowledgeable on the ASIC or IP verification flows, have a good understanding of different methodologies, particularly SystemVerilog UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenges, contribute to define the verification plans and execute the required verification tasks.

Your Key Responsibilities

• Verification specialist working on customer and internal projects.


• Provide verification contribution or leadership to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.


• As a member of the verification team you would also be responsible for contributing to the verification strategy and plans, the architecture of the test environment and its complete execution. architecting and development of the complete test environment.


• Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers.

Your Key Skills and Experience

• 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 group University.


• 2+ years’ experience in industry working on a variety of verification projects.


• Good knowledge of verification methodologies particularly UVM and SystemVerilog.


• Experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog.


• Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests.


• Good knowledge VHDL/Verilog RTL.


• Good understanding of modern verification flows and methodologies.


• Ideally you will be familiar with either Mentor Questa or Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows.


• Understanding of functional safety and quality processes, to achieve ISO26262 or similar standard’s compliances will be considered as a plus.

About You

• Good communication and interpersonal skills, which enable you to interface easily and effectively with cross-functional stakeholders in an international environment.

• Self-motivated achiever who gains satisfaction from providing excellent customer service and has a ‘can-do’ attitude.

• Happy to take ownership of issues and provide suitable solutions.

• You think holistically, are creative, and have a quick grasp, which enables you to maintain an overview in complex situations and make well-founded decisions.

• A team player, ideally with experience collaborating within the international, cross-functional environments.


• Adaptable and wiling to embrace change.

Position Specifi

This role is flexible, some UK and  international travel required.

You must have the right to live and work in the country you have applied for.