Principal Technical Program Manager

About Graphcore

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary

As a Technical Programme Manager, you will lead the planning and delivery of complex silicon chip design programmes, focusing on execution across design, implementation and tape-out. You will work across the full development lifecycle, from early product definition through to production readiness.

You will partner with engineering managers and cross-functional teams (ASIC/SoC design, physical design, verification, DFT, CAD, product and operations) to ensure programmes are delivered on time, within scope and to a high standard. This role requires strong technical understanding, programme leadership, and the ability to manage dependencies in a fast-paced semiconductor environment.

The Team

Our Engineering Programme Management team sits at the heart of silicon innovation, enabling delivery of advanced chip technologies. We work across architecture, design, implementation and operations to drive alignment, execution and continuous improvement throughout the silicon lifecycle.

Key Responsibilities

• Lead planning, execution and day-to-day management of silicon design programmes, ensuring milestones and dependencies are clearly defined and tracked.


• Build and maintain integrated schedules across architecture, RTL, verification, physical design, DFT, CAD and tape-out.


• Drive alignment across engineering, product and operations on scope, priorities, resourcing and delivery plans.


• Support execution through key phases including specification, design reviews, implementation, sign-off and tape-out readiness.


• Manage scope changes, assessing impact on schedule and resources while maintaining stakeholder alignment.


• Identify risks, dependencies and challenges early, with clear mitigation and escalation plans.


• Coordinate cross-functional readiness for major milestones such as IP integration, design closure and tape-out.


• Provide regular updates on programme status, risks and recovery plans.


• Drive structured decision-making and accountability across teams.


• Capture lessons learned to improve programme management practices and workflows.

Candidate Profile

Essential

• Bachelor’s degree (or higher) in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or a related field.


• 3–5 years’ experience in programme/project management or technical delivery within semiconductor, ASIC, SoC or hardware environments.


• Experience supporting silicon design programmes across RTL, verification, physical design and tape-out.


• Good understanding of the silicon development lifecycle, including design, integration, implementation and tape-out milestones.


• Experience working with cross-functional engineering teams.


• Strong organisational and planning skills, with the ability to manage dependencies and competing priorities.


• Strong problem-solving skills with a proactive approach to risk and issue management.


• Excellent communication and stakeholder management skills across technical and non-technical audiences.


• Self-motivated, collaborative, and effective in fast-moving environments.

Desirable

• Experience with ASIC/SoC development flows, including design reviews, implementation, sign-off and tape-out.


• Familiarity with RTL, physical design, DFT, CAD or silicon platform teams.


• Understanding of system-level considerations influencing chip design.


• Experience in AI, accelerator, datacentre or high-performance compute silicon programmes.


• Knowledge of semiconductor product development from concept to manufacturing handoff.