Senior RF/Analog ASIC Design Engineer

Job DescriptionThe Senior RFIC Design Engineer will be responsible for block level design in Ku/Ka band RF Receivers & Transmitters for next generation of satellite communications in deep sub-micron technologies. You are responsible for architecture design, circuit design & verification, review for RFIC building blocks like PA, Phase Shifter, Active VGA.You will develop new circuit architectures, design/verification methodologies to deliver ASICs that meet all the performance requirements in the required timeline. While the job primarily involves you to own block level designs, you will work closely with the layout engineer to ensure the layout meets all the constraints for the best silicon performance.The ideal candidate will typically have 3 years of experience in the design of RFICs with at least one tape-out experience in deep sub-micron CMOS technology.Technical Responsibilities: Responsible for circuit design for RFIC building blocks.Delivering high quality RF/Analog blocks with leading edge performance using innovative architectures and circuit implementations with guidance from Senior design staff.Work closely with the layout team on IP floor-planning, trial layout design, parasitic extraction, and modifications. Document own work and actively participate in design reviews.Organisational Responsibilities:Ongoing development of core competencies & technical skillsReceptive and agile to the project needs.Good estimation of timescales for own tasksFollow good engineering practices including processes, documentation, tools & automation.Identify risks, flag issues in a timely manner so own milestones are achieved.Qualifications & Skills:Essential:

An Engineering degree in a relevant discipline Typically 3+ year experience in RFIC CMOS circuit design and processes (preferably 15GHz or higher operating frequencies) – including more than 1 successful tape-out.Cadence Virtuoso Design Framework ExperienceAbility to work, interact and collaborate within the ASIC team.Great communication skills and able to take responsibility for delivery of own designs to tight timescales.Desirable:

Experience in 22nm FDSOI or other sub 45nm CMOS process nodes for RF/High speed ICsExperience with process relating to production release and qualification.Experience in EM modelling tools such as RFPro or EMX Experience in LNA design and RF PAUnderstanding of Radio systems, gain and noise budgeting, phase noise and intermodulation mechanismsExperience in RFIC CharacterisationExperience in Chip ESD design & qualification