We are looking for a Senior FPGA Design Engineer to join the development team. You will form part of the team creating industry leading hardware products.
Key Responsibilities
• Design and verification of FPGA code for a range of hardware products including high-speed motion capture and video cameras, calibration devices and synchronisation and networking equipment.
• Ensure all FPGA designs achieve required level of timing closure and functional performance before release.
• Code reviews of existing and new VHDL/Verilog files.
• Working alongside a team comprising of electronic, mechanical and software design engineers in the creation of high performing and cost-effective solutions.
• Ensuring designs have appropriate test coverage for development and manufacture and that designs meet appropriate regulatory compliance.
• Full product lifecycle involvement from early conceptual studies through to manufacturing support post-release.
Required Skills, Knowledge and Expertise
• Strong demonstrable experience in VHDL including implementation of algorithms. Verilog experience an advantage.
• Experience in compilation timing closure is essential.
• Working knowledge of interface standards such as LVDS, PCIE, GMII etc
• Skilled in testbench generation and verification on new design features
• Competent with Version Control System tools, like Git, SVN, etc
• A knowledge of high-speed digital design, a working knowledge of analogue design and experience of developing products for manufacture with an emphasis on DFM/DFT would be advantageous.
• Suitable candidates will be educated to degree level in Electronic Engineering (or equivalent) with demonstrable and relevant industry experience.
• A working knowledge of image sensors, optics, Ethernet and RF Design would be advantageous, as would using AI to augment your work.
We’re looking for an outgoing, confident and self-motivated candidate that will be a great fit within our small and highly experienced team of engineers Only candidates based in UK and eligible to work in UK are allowed
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